This invention relates to computer processors and in particular to distributed integrated circuit signal processors that are dynamically reconfigurable.
A current direction of development in computer technology is towards dynamically in-use reconfiguration in lieu of down-time reprogramming and software redirection of processors for computing. Known developments of configurable and dynamically reconfigurable computing to date fundamentally employ computer architecture such as field-programmable gate arrays (FPGA) of conventional logic gates in combination with conventionally programmable computers. There are no known computer processors having an integrated circuit of basic operating modules of computers in communication with an integrated circuit of communications buses in a manner taught by this invention.
An example of present reconfigurable computing is FPGAs that contain memory and arithmetic processing units but that are limited to use with special-purpose blocks of circuitry has been under development recently at Massachusetts Institute of Technology by Andre DeHon and Thomas F. Knight Jr. Another example is a dynamic instruction set computer (DISC) in which a conventional microprocessor has been combined with an FPGA by Brad L. Hutchings at Brigham Young University.
Additional examples of different but related developments in reconfigurable computing are described in the following patent documents. U.S. Pat. No. 5,600,845, issued to Gilson on Feb. 4, 1997, is limited to use with a "personal computer" as a "host" for "programming means defining an appropriate mode of operation of a gate array" (FPGA) as stated in its independent claims. The programming means are employed also to program input/output (I/O) blocks, logic blocks of conventional gates and routing resources. The Gilson patent describes a reprogrammable coprocessor, not a processor architecture which can function independently of an auxiliary computer as taught by this invention. In addition, the Gilson patent is limited to a core with a reduced instruction set computer (RISC) in a slave relationship to a master host processor instead of equal processor elements being contained in a central processing unit as taught by this invention. Dependance of the Gilson device on programming by a host computer may aid its versatility in comparison to some reconfigurable FPGAs but confines it to software limitations which are eliminated by this invention.
U.S. Pat. No. 5,535,406, issued to Kolchinsky on Jul. 9, 1996, describes and illustrates a Netlist type of computer with a processor module containing FPGA employing conventional gates that it recommends as a "virtual processor module" for variable hardware functions. Independent claims 1 and 8 in the Kolchinsky patent list components with widely inclusive features not having architectural or working relationship to each other.
Neither describing nor illustrating computer architecture or working relationships of features other than a Netlist type of computer and FPGA with conventional gates for a "virtual" processor module, the Kolchinsky patent is limited to those features in the context in which they are described. It does not include a more broadly inclusive "reconfigurable, programmable logic matrix array" nor more broadly inclusive "programmable processing elements" than it describes or otherwise teaches. Claims 2 and 9 of the Kolchinsky patent specify that the "programmable logic matrix array comprises a plurality of programmable processing elements" but with description of FPGA of primarily a Netlist type of computer. Further, in light of extensive technical discussion of FPGA and Netlist related components with complexity of programming a core of low-level elements that the Kolchinsky patent did describe, other architecture and features in relationship to "programmable processing elements" would have been described and discussed also if they had been anticipated for the Kolchinsky patent.
The Kolchinsky patent did not describe the distributed, dynamically reconfigurable signal processor with a two-layered array of clustered basic operational modules as taught by this invention. Instead of FPGAs, the present invention describes architecture of a functionally complete processor based on a central processing unit having a core to which all computational resources are accessible for high specific computing density with a high degree of reconfigurability for a wide selection of classes of applications. Instead of conventional OR or AND gates employed in field programmable gate arrays, functionally intelligent modules with ALU capability and/or memory registers are distributed with integrated circuitry for a central-processing functional unit structure that makes application of algorithms much easier and more transparent for a user with this invention.
An additional difference from the FPGA "virtual" process of the Kolchinsky patent relates to time for reprogramming and switching functions which are critical to most applications of reconfigurable computing. FPGA is a relatively fine-meshed logic structure. Although some forms of FPGA are finer than others, all require immensely more time than a distributed "chunky" system employed by this invention to accomplish computational functions.
Further yet, this invention allows dynamic reprogramming of the core during operation. This is not possible with the Kolchinsky virtual processor or with other known reconfigurable processors.
U.S. Pat. No. 5,689,661, issued to Hayashi, et al. on Nov. 18, 1997, describes switching technology for a reconfigurable network of processors.
U.S. Pat. No. 5,361,367, issued to Fijany, et al. on Nov. 1, 1994, describes robotic computation that specifically requires a host computer that is not required by this invention.
U.S. Pat. No. 5,020,059, issued to Gorin, et al. on May 28, 1991, describes switching technology for processor elements which are obviated by the central processing unit of this invention.
U.S. Pat. No. 4,748,585, issued to Chiarulli, et al. on May 31, 1988, describes partitioning of arithmetic logic units (ALU) that also is obviated by this invention.
A known alternative to reconfigurability for enhanced adjustment of computer capability is parallel processing, such as described in U.S. Pat. No. 5,535,408, issued to Hillis on Jul. 9, 1996. Instead of adaptive reconfiguring as taught by this invention, it provides oversupply of computer capability with a high plurality of separate integrated circuit chips that can be accessed quickly with parallel communication for algorithmic adaptability. It is too different for novelty comparison.